1. Star ModelSim and Make filelist
Star your modelsim and change the directory to youre project folder.
Use “pwd “ to show your current directory.
Use “cd d:verilog “ to change directory.
Use “dir *.v /b/s >filelist.f “ to make file list.
The file list is as follow, which contains all the .v files under current folder ,including file in subfolders.
Tips: if codes are written in Verilog HDL , there is no need to adjust the sequence of the filelist , while in VHDL, some files should be compiled first , so the filelist sequence may need some adaptation.
3. create your modelsim .lib and .work.
change the directory to youre project folder ,and copy filelist.f there.
Here we “cd projects”
Use “vlib work “ to build work lib.
Use “vmap work work “ to map work lib.
5. start simulation and check the coverage
start simulation with “vsim – coverage work.top” and “run 10us “ for some time.
And you can see the coverage like this.
More detailed coverage information is as follow,
You can get all the coverage information here . If you have any problem in the use of modelsim coverage ,please contact me and I am glad to help .