Quick Guide to using the Allegro to ExpeditionPCB translator.
Nigel Aves, September 2004.
The Allegro side of Translation.
Load the Allego.brd file that needs to be translated into Allegro. The SKILL scripts supplied with the release already have built in the ability to generate the files required to run the translator. After loading the SKILL files instead of DCAD OUT you must use MAIN OUT.
skill load “dfl_main.il”
Choose “One Way” from the dialogue.
When the following dialogue appears
choose “Cancel” . The Via Identification File is used as a “last resort” to manually specify the padstack names of vias, fiducials and mounting holes. Typically this file is not needed now as we have spent a lot of development time identifying these objects automatically.
Once the SKILL script has finished running you will find that it has create the required _MGC directory and all the needed files for the translator. (Under no circumstances must the devices directory be moved or deleted, this is the directory that contains all the electrical data that the PDB is built from. It’s also worth mentioning that designs should be translated from different root directories to ensure that only the devices for that design are in the \devices directory)
Extracting the rules_tmp.dcf and ecsetaudit.rpt
Major changes have been programmed into both DFL-mode and the translator for the translation of High Speed rules. Cadence has adopted the Electrical Spreadsheet as their de-facto standard for entering these types of rules. Because they are more complete and understandable we are now adopting the ability to read an extracted (exported) electrical spreadsheet.
To do this :-
1/ Setup >> Electrical Constraints Spreadsheet << In Allegro (Designer or Expert)
2/ File >> Export >> Constraints << Constraints Spreadsheet
Please note that this file should be written into the \work directory just created by the initial SKILL scripts. The file MUST be called rules_tmp.dcf
This file contains all of the High Speed rules and defines all pin pairs with rules. From this file we are able to extract “Electrical Nets” and from this we are able to process any rules against these nets. The downside of process Electrical nets is that the formulas dialogue becomes almost impossible to comprehend.
3/ Audit >> Electrical Csets << Constraints Spreadsheet
Please note that this file should be written into the \work directory just created by the initial SKILL scripts. The file MUST be called ecsetaudit.rpt (this is the default name no matter what the job is called)
This file contains all information that we need, to correctly set the topologies on a net if it has been created using SpectraQuest.
You have now finished all of the tasks required on the Allegro side.
We have an outstanding issue that in Allegro they define “0” sized pads, we have not corrected all of the possible cases, what we do is make them as small as possible (1 DBU) and put a message in the log file.
HKP error messages are not the best in the world; sometimes you get an exact line number and other times a section is reported. Read the message carefully and try to find the error. Beware of editing HKP files. These files must contain NO formatting errors.
Typical errors are when we have a padstack defined but used as multiple types (mounting hole, fiducial, via, padstack). This is the most common of problems found when importing padstacks and cells. The best solution is to copy to a new name (Round020_MT from Round020) and then make the required changes to the cell.hkp file. (Typically you can import the padstack.hkp and make these changes using the Padstack editor in ExpeditionPCB. Now you can run the cell.hkp and from the messages easily track down the padstacks that need to be changed.)
If this is your first experience with 2004(.1) – DFL-mode; please note that the SKILL scripts must now be run from an Allegro recognized SKILL directory. This can be the active directory that the .brd file is located in or typically the Allegro generated directory PCBENV .
During the translation process the cells generated do contain all the relevant information from Allegro. (Notes etc).
To successfully translate a “board outline” the element in Allegro must be contiguous, unfortunately we have discovered many designs where this is not true. Please check the board outline in Allegro to ensure that there are no gaps.